module try();

reg clk = 0;
always #5 clk = ~clk;

reg [2:0] cnt = 0;

reg flag = 0;

always @(posedge clk) begin 
    cnt <= cnt + 3'b1;
    if(cnt == 3'b111) begin 
        flag <= 1;
    end
    else if(cnt == 3'b001) begin 
        flag <= 0;
    end
end

initial begin 
    $monitor("At time %t: cnt = %b, flag = %b", $time, cnt, flag);
    #200 $finish;
end

endmodule
